ECE 2212

EXPERIMENT 6

25 October, 1 November, 8 November 2012

MOSFET I-V Characteristics and MOSFET Circuits

PURPOSE

The purpose of this experiment is to measure the I-V characteristics of an N-channel MOSFET, a P-channel MOSFET, the input/output characteristic of a CMOS inverter and the operation of several other MOSFET circuits including:

Ø NMOS Inverter with a Resistive Load

Ø NMOS Inverter with an Active Load

Ø Two-Input NMOS NOR Gate with a Resistive Load

Ø CMOS inverter circuit biased as a small-signal amplifier.

Ø Measure the I-V characteristics of both an NMOS and PMOS transistor on the CD 4007 array.

NOTE

Because of the number of different circuits, this is a three week experiment and the report is to be a maximum of 9 pages (instead of 3 pages) plus a cover page which includes a well-written and comprehensive abstract. This report will be evaluated on a 60-point scale. The report will be due on Thursday, 15 November.

COMPONENTS

Ø CD4007 MOSFET array

Ø 0.01mF capacitor

Ø 3.3 kW resistors

PRELAB

Prepare a detailed circuit diagram in your notebook of how you will connect an NMOS and PMOS for measuring the I-V curves. Study the material in Chapter 4. A complete manufacturer’s data sheet has been posted on the class WEB page.

The device you will use throughout this experiment is a CD4007B Transistor array. It contains three N-channel and three P-channel devices. Detailed schematic diagrams and pinouts are available on the data sheet. Please use care when working with these chips. They are very susceptible to excessive voltage and ESD (Electro-Static Damage). Do not exceed the experiment settings in an attempt to make your experiment work. The pin configuration is given in Figure 6.1. Note that you will be using the CD4007B which have a lower maximum voltage rating than the CD4007UB. The diagrams are the same for both the “B” and “UB” suffix devices. Avoid exposing the chip to ESD (electrostatic damage). This time of the year often has low relative humidities which make ESD more of an issue. Do not exceed the V_DD maximums!!!

Study the I-V curves provided in the data sheets so that you have some idea of what to expect.

Figure 6.1 Pin Configuration of CD4007.

Warning: Pin 14 should always be connected to the most positive dc voltage in the circuit. Pin 7 will always be connected to the most negative dc voltage in the circuit

(or else )!!!

PROCEDURE

I-V Characteristic of an N-channel MOSFET

Ø Connect the circuit shown in Figure 6.2. Remember to connect pin 14 to the +8V supply. Pin 7 is shown connected to ground. The mA meter should be a digital multimeter set to an appropriate scale. Use the voltage readout on the power supply as you adjust V_DD to +8 volts. Use the NFET connected to Pins 6, 7, and 8.

Figure 6.2 Transfer Characteristic Measurement For an NMOS

Ø Before turning on the power supplies, check your circuit wiring carefully. Use the 0 to 6 volts adjustable supply for V_GS. Be sure that the V_GS supply is turned down to zero. Vary V_GS from zero in the positive direction. Carefully watch the value of the drain current. When the current becomes nonzero (in the vicinity of 1.5V), you should start taking measurements of V_GS at selected values of I_D. Record the values of V_GS at I_D = 0.01, 0.05, 0.10, 0.50, 1 and 2 mA, . Adjust I_D to the specified value, or at least close, then record the value of V_GS. Note that I_D = 10mA; this is the maximum rated value for this chip. Plot data as you proceed.

Ø Plot your data and use a linear regression (least squares fit) to extract values for VTO, LAMBDA, and KP and develop a SPICE model that compares well with your measured curves. To generate these curves, you will need to report your measurements at several values of V_DS, that is at several voltages other than 8 volts. You will have to assume W/L=1 because you do not know the actual values of W and L and then adjust KP accordingly. This model development from your parameter extractions should be included in your report. Write a Shichman-Hodges model equation for your NMOS.

I-V Characteristic of a P-channel MOSFET

Ø Use the PFET connected to Pins 6, 13, and 14. Note that Pin 13 is the PFET drain.

Ø Before turning on the power supplies, check your circuit wiring carefully. Your ammeter connects from Pin 13 to ground. Pin 14 is adjusted to 8 volts. When you do this, V_DS is negative which is what you want. Be sure that the V_GS supply is turned down to zero. Vary V_GS from zero in the negative direction. Carefully watch the value of the drain current. When the current becomes nonzero (in the vicinity of V_GS = -1.5V), you should start taking measurements of V_GS at selected values of I_D. Record the values of V_GS at |I_D |= 0.01, 0.05, 0.10, 0.50, 1, and 2 mA. Adjust I_D to the specified value, or at least close, then record the value of V_GS. Note that `|I_D| = 10mA; this is the maximum rated value for this chip.

Ø Note that for P-channel MOSFET, the V_GS voltage source is connected in an opposite way to that of Figure 6.2. Also observe that V_DS is also negative.

Ø Plot your data and use a linear regression (least squares fit) to extract values for VTO, LAMBDA, and KP and develop a PSPICE model that compares well with your measured curves. To generate these curves, you will need to report your measurements at several values of V_DS, that is at several voltages other than |8| volts. You will have to assume W/L=1 because you do not know the actual values of W and L and then adjust KP accordingly. This model development from your parameter extractions should be included in your report. Write a Shichman-Hodges model equation for your PMOS.

THIS IS A GOOD PLACE TO END WEEK ONE- Proceed If You Have Time

Refer to the three circuit diagrams in Figures 6.5, 6.6, and 6.7. All will operate with a VDD = +8 volt power supply. Remember Pin 14 should always be connected to the most positive dc voltage in the circuit. Pin 7 will always be connected to the most negative dc voltage in the circuit

1. Set up the NMOS Inverter with a Resistive Load as shown in Figure 6.5. Use the NFET connected to Pins 6, 7, and 8. Plot the transfer characteristic. Identify the saturation, ohmic, and cutoff regions of operation. Suggest a Q-point to obtain the largest small-signal voltage gain. Verify your experimental results with a load line and SPICE simulation. You will need your model parameters as obtained earlier in this experiment. Observe that you will need to provide a dc offset from the signal generator.

2. Set up the actively-loaded NMOS Inverter as shown in Figure 6.6. Use M1 Pins 6, 7, and 8 and M2 Pins 3, 4, and 5. Plot the transfer characteristic. Identify the saturation, ohmic, and cutoff regions of operation for each FET. Suggest a Q-point to obtain the largest small-signal voltage gain. Verify your experimental results with a “load line” which consists of the M2 characteristic and SPICE simulation. Compare your results with the resistively-loaded circuit. You will need your model parameters as obtained earlier in this experiment. Note that this circuit is different than the depletion mode inverter circuit discussed and “SPICED” in class.

3. Set up the resistively-loaded two-input NOR gate as shown in Figure 6.7. Use M1 Pins 6, 7, and 8 and M2 Pins 3, 4, and 5. VIN1 should be an adjustable dc voltage source between 0 and 8 volts. VIN2 should be a 0-8 volt square wave. For several values of VIN1 between 0 and VDD = 8 volts, plot the transfer characteristic. Identify the saturation, ohmic, and cutoff regions of operation. Verify your results with a SPICE simulation. By studying vo(t), verify NOR Gate operation

THIS IS A GOOD PLACE TO END WEEK TWO- Proceed If You Have Time

Ø Pin 14 should always be connected to the most positive dc voltage in the circuit. Pin 7 will always be connected to the most negative dc voltage in the circuit

Ø Connect the CMOS inverter circuit of Figure 6.8. You can also use the CMOS inverter FETS connected using Pins 9, 10, 11, and 12 or the FETS connected with the pins shown in Figure 6.8. Connect the input and output to the horizontal and vertical inputs (respectively) of your oscilloscope set to the x-y mode. This arrangement allows you to display the transfer characteristic of the circuit. Before connecting your function generator to the circuit input, adjust it for a 0-10 V triangular waveform at a frequency of 1 kHz. You will need to use the dc-offset control on your function generator to do this. That is a 10 volt peak-to-peak triangular wave added to a 5 volt dc offset. Observe and sketch the transfer characteristic, recording all critical values of voltage. Your alternative is to use a + 5 and –5 volt power supplies (which will work fine) if you choose not to use a 5 volt offset on the input signal.

Ø Your report should include a PSPICE simulation of this circuit using your parameter extraction NMOS and PMOS models. Compare to the data sheets.

Figure 6.8 CMOS Inverter

Ø Measure the pulse response of the CMOS inverter as shown in Figure 6.9. The capacitor C_o has been added to “slow down” the output waveform so that measurements can be more easily made. Since the input of a CMOS gate is primarily capacitive, this also will provide the output behavior when a CMOS gate is driving many other CMOS gates (a capacitive load). Adjust your function generator to 0-10V square wave at a frequency of about 10 kHz, then connect it to the input. Measure the rise and fall times of V_out(t). You should be able to compute the effective value of the CMOS inverter output resistance from the rise and fall time measurements. Refer to what you did in Experiment 1 for a basic R-C network.

Ø Compare your measured results with a PSPICE simulation.

Figure 6.9 CMOS Inverter With Capacitive Load

A few more items to think about. Compare the static power dissipation of the four circuits CMOS Inverter, NMOS Inverter with a resistive load, NMOS inverter with an active load, and the NMOS NOR gate with a resistive load) when operated as switches/inverters as opposed to amplifier operation.

I now make my own coffee and have a nice slide rule collection in my office.

And in recognition of the WINDOWS 8 Release