EE 2212

Problem Set 8

WILL NOT BE COLLECTED

Study Guide For The Final Exam

S. G. Burns

Final Exam 15 December, Wednesday, 10:00-11:55

NOTE 1: These are typical of what you may find on the Final Exam since we have not had any weekly quizzes on these important topics!!! It is quite probable that one or more of these problems or parts of these sample problems would be on the Final Exam.

NOTE 2: I will have ZOOM Office Hours that I will post daily

NOTE 3: Additional information about other topics to be covered on the Final Exam will be discussed in our last class on Friday, 10 December

NOTE 4: Obviously I can not and do not intend to cover all of the questions and topics in the study guide problem set but wprking these problems is a good idea.

1. Text 15.1 BJT Differential Pair Rid and Ric can be ignored. Problems 1 and 2 are very similar.

2. Text 15.4 BJT Differential Pair Similar to Text 15.1 Rid and Ric can be ignored

3. Modified from an old quiz. Refer to the modified and annotated partial diagram of a Fairchild μA725 operational amplifier integrated circuit. Assume all npn BJTS are matched with β = 150 and an Early voltage of V_A = 100 volts. I_C3= 31 μA. The circuit is connected to ± 12 volt power supplies. Compute the following quantities for this circuit (Observe, you will have to compute a value for R₄from the Widlar design equation).

(a) The differential mode voltage gain, A_dm.

(b) The common-mode current gain, A_cm.

4. Assume a Class B audio amplifier operating between ±48 volts and driving a 4 W speaker. Neglect the effect of crossover distortion.

ClassBNr1 - Copy

(a)Provide required maximum ratings as indicated for the transistors using a well-labeled sketch of the back-to-back load lines to illustrate your answers.

I_{C(max) =} ____________ V_CE(max) = ___________ P_C(max) = __________

(b) Design a protection circuit to limit the transistor to the I_{C(max) you} computed in part (a) should the amplifier output be short-circuited. Incorporate this protection circuit in your basic Class B circuit diagram.

5. Amplifier Analysis

A partial circuit diagram for a Fujitsu MB 47358 operational amplifier is given below. Assume V⁺ = 15 volts and V^- = -15 volts. For the npn transistors, assume β = 150, V_BE(on)= 0.7 Volts, and V_AN = 100 Volts. For the pnp transistors, assume β= 100, V_BE(on) = 0.55 Volts, and V_AP = 50 Volts.

(a) Briefly describe the circuit function/operation of :

Q₁₀ and Q₁₁

Q₁₃ and Q₁₄ (Diode connected transistors)

Q₇ Circuit topology

Q₅ and Q₆

(b) Assume a sinusoidal input voltage that results in an output voltage v_o(t) = 12 sin (ωt) volts. R_L = 1 kΩ.

Compute values for :

1. Peak and average power to the load resistor.

2. Resultant collector efficiency.

3. Power required from the power supplies for the output stage.

4. A design value for R_SC to limit the short circuited load current to 30 mA .

(c ) Estimate the following :

Collector currents in Q₅and Q₆

Collector currents in Q₁ and Q₂

Voltage at the base of Q₅ and Q₆

Voltage at the emitter of Q₇

final2003

6. Excerpted From an Old Quiz

Answer the following questions for this power amplifier.

Sketch and label the Back-to-Back load lines for Q₁and Q₂. From your sketch, provide numerical values for:

I_{C(max)
_}______________ , V_CE(max)___________, and P_C(max)______________

(a) __________If v_in(t) = 12 sin(ωt) volts , what is the peak power delivered to the 4 Ω load?

(b) __________If v_in(t) = 12 sin(ωt) volts , what is the average power delivered to the 4 Ω load?

(d) __________If v_in(t) = 12 sin(ωt) volts, compute the Collector Efficiency, η_C.

(e) __________If v_in(t) = 12 sin(ωt) volts, how much power is being dissipated in Q₁and Q₂?

(f) __________If v_in(t) is a ±12 volt square wave, estimate the Collector Efficiency, η_C.

(g) Q₃ and Q₄will (Circle all that apply):