All MIPS instructions are 32 bits, or 4 bytes, long. The fixed length is almost universal in RISC processors. The 32-bit size is currently the most common size. This could change in a few years.
When MIPS instructions are classified according to coding format, they fall into four categories: R-type, I-type, J-type, and coprocessor. To a large extent,these formats determine the execution activities in processor circuitry. Later, these instruction categories will be refined into instruction types that take into account the different ways that instructions make use of the fields of the instruction.
This web page does not attempt to describe all MIPS instructions. The following types of instructions are not dealt with.
In order to deal with shifts and rotates it is assumed that the ALU contains some additional circuitry (typically a barrel shifter) for these operations and has control signals that can select these operations along with add, subtract and bitwise operations.
This coding group contains all instructions that do not require an
immediate value, target offset, memory address displacement, or memory
address to specify an operand.
This includes arithmetic and logical instructions with all operands in
registers, shift instructions, and the register jump instructions
jalr and jr.
All R-type instructions use opcode 000000.
The I-type coding group includes arithmetic and logical instructions with an immediate operand, branch instructions, and load and store instructions.
All opcodes except 000000, 00001x, and 0100xx are used for I-type instructions.
The J-type coding group consists of the two non-register jump instructions
j and jal.
These instructions require a memory address to specify their operand.
J-type instructions use opcodes 00001x.
Execution of all MIPS instructions involves at least the first three of the following activities. The last four activities are required for some, but not all, instructions.
The program counter (PC) hold the address of the next instruction. The arithmetic-logic unit (ALU) performs arithmetic and logical operations such as adds, subtracts, bitwise AND and OR, along with shift and rotates.
The activities are approximately in time order. However, PC update may be done in two steps with the last step done after an ALU operation. Also, some of the activities can be overlapped in time.
The organization of the data path can be determined from these activities. Where an activity requires selecting among different options depending on the instruction, there will be a multiplexer that selects the appropriate option as directed by a control signal.
The contents of the program counter (PC) are used as an address sent to instruction memory. Fields from the fetched instruction are sent wherever they are needed. Instruction fetch is the same for all instructions.
The PC gets a new value selected from the following.
PC update may be done in more than one step. Processors typically do a simple increment (PC ← PC + 4) automatically, then make later modifications for branches, jumps, and interrupts.
The MIPS single-cycle implementation diagram does not include signal handling for register jump target addresses or interrupt addresses.
Instruction decoding produces controls signals for the datapath and memory. The inputs to control circuitry are the opcode and function fields of the instruction. It generates the following kinds of control signals.
Instruction decode is the same for all instructions.
The ALU is designed to combine two source operands to produce a result. The source operand fetch activity fetches the two source operands. One source operand is always the register specified by the rs instruction field. The other is selected from the following.
The MIPS single-cycle implementation diagram does not include signal handling for the zero-extended immediate instruction field. It is only used in a few unsigned integer instructions.
The ALU can be used in three different ways:
The main control block only decodes the opcode bits of the instruction. When these bits are not all 0 the ALUOp signal from the main control block specifies the ALU operation and this signal is passed to the ALU without modification.
When the opcode bits are 000000 it indicates that the instruction is an R-type instruction. Then the function (fn) bits specify the operation performed by the ALU. The ALUOp signal is then just a special code that indicates that the ALU Control block should determine the ALU operation from the function bits.
A read or write control signal is sent to memory. The result from the ALU is used as an address. For a store, the value written to memory comes from the register specified by the rt field of the instruction.
Some instructions, such as branches, jumps, and stores, do not write to a register. For the instructions that do write to a register, the destination register can be one of the following.
The MIPS single-cycle implementation diagram does not include signal handling for $ra.
The value to be written to the register can come from the following places.
The MIPS single-cycle implementation diagram does not include signal handling for the incremented PC.