There are two basic types of routing elements: multiplexers and demultiplexers. Multiplexers are much more common in high-level views of processor circuitry.
A multiplexer is a combinational (stateless) logic circuit for selecting among several possible input signals. Patterson and Hennessey use the symbol to the left for a multiplexer.
This multiplexer has four signal inputs: W,
X, Y, and Z.
A multiplexer can in principle have any number of signal inputs.
The control or select input Sel determines which of
the signal inputs appears as the output Out.
It has as many bits as needed for the selection.
One bit suffices for just 2 signal inputs, 2 bits suffices for 3
or 4 signal inputs, and 3 bits suffices for 5 to 8 signal inputs.
The multiplexer output Out can be a multi-bit signal.
Each of the signal inputs has the same number of bits as the output.
The multiplexer implementation uses an AND gate for each data input. This AND gate is configured to control its data input — pass it to the output only when the select signal matches its input number. The AND outputs are then combined with an OR gate.
If the multiplexer has multi-bit input and output data signals then this circuitry is repeated once for each bit. The select signal is connected to each replication.
A demultiplexer routes a single data input signal to one of several different data outputs. That is, one of its outputs is identical to the data input signal, while the other output signals are 0. The output that matches the input signal is determined by a control input signal.
A demultiplexer can in principle have any number of data outputs. The control input has as many bits as needed for the selection. One bit suffices for just 2 data outputs, 2 bits suffices for 3 or 4 data outputs, and 3 bits suffices for 5 to 8 data inputs.
The demultiplexer data input can be a multi-bit signal. Each of the data outputs has the same number of bits as the input.
Demultiplexers play an important role in the write ports of register banks — they route the write enable signal to the appropriate register. By doing so, the demultiplexer determines which register gets data written to it.
The demultiplexer implementation uses an AND gate for each data input. This AND gate is configured to control the data input — pass it to the output only when the select signal matches its input number.
If the demultiplexer has multi-bit input and output data signals then this circuitry is repeated once for each bit. The select signal is connected to each replication.