Review for Midterm 2

1. What are temporal and spatial locality? What are some aspects of typical programs that contribute to temporal and spatial locality with regard to instruction access? What are some aspects of typical programs that contribute to temporal and spatial locality with regard to data access?
2. Describe the spectrum of placement strategies used in the memory heirarchy. What strategy is used for virtual memory? What strategies are used for caches? Why is there a difference?
3. What strategy is used for locating blocks in virtual memory? What strategy is used for locating blocks in fully associative caches (such as a small TLB)? Why is there a difference?
4. A computer has a 8-way associative 256 KByte cache. Each cache block is 32 bytes. The 64MByte main memory is byte addressable. How many bits are in the tag, set/index, and offset fields of a memory address?
5. Describe how each of the cache addressing fields is used in a memory read.
6. What is a translation look-aside buffer? Why is it important?
7. A processor has 32GB byte addressable virtual address space. The page size is 8KB, and all page table entries are 4B. A process uses 2MB at the low end of memory and 64KB at the high end. What is the total amount of memory used for the page tables for this process using the following schemes?
   1. single level, single segment page tables
   2. single level, two segment page tables
   3. two level, paged page tables
8. In each part of the previous problem, how many memory acceses are required each time the program accesses a data item? Is this a problem? Why or why not?
9. Describe two common strategies in a memory heirarchy with regard to replacing blocks. What strategy is used for virtual memory? What about caches?
10. Describe the two write strategies in a memory heirarchy with regard to handling write hits. What strategy is used for virtual memory? What is the trend for caches?
11. What is cache coherence? Describe a situation where it is a concern.
12. Can programmers use their understanding of caches to improve program performance? Give an example.
13. The trend in cache design is to use more cache levels. For example, processors in 1997 only had two cache levels but more recent processors have three levels. Why?
14. Why is average memory access time not a good measure of memory hierarchy performance in a system with an out-of-order (e.g. register renaming) processor?
15. Describe the characteristic of modern DRAM that makes caching more effective.
16. Why does higher associativity result in lower miss rates?
17. What are compulsory misses? What are capacity misses? What are conflict misses?
18. In a system with both a cache and virtual memory, virtual memory address translation can occur either before or after the cache. That is, the addresses in the cache can either be physical or logical. Which is preferable? Why?