ECE 2212

EXPERIMENT 6

(Revised 1 November 2013)

MOSFET Circuits

Revision 1: Figure 6.3 was changed to align more closely with the text.

Revision 2: Include KP=5E-4 in both the NMOS and PMOS “MODEL” statements to better match device specifications from the default break models.

Note 1: I will be hosting Mat Johnson from GeaCom and Greg Carpenter and Dan Landherr from Boston Scientific on 31 October and 7 November respectively. This means that I will be minimally present in the 10:00-11:00 time period during the 10:00-1:00 laboratory.

Note 2: Consequently, Experiment 6 is designed to require about 4 laboratory hours. Experiment 6 is therefore scheduled for Thursday, 31 October , and Thursday, 7 November.

Note 3: Experiment 6 will be scored using the 40-Point rubric.

Note 4: Experiment 6, six page maximum not including the cover page. Due on Wednesday, 13 November, in class.

Note 5: The Department of Electrical Engineering Industrial Advisory Board is scheduled for Thursday, 14 October, consequently I am cancelling lab !!!

PURPOSE

Measure and simulate the transfer characteristics (input/output characteristics) of:

Ø NMOS Inverter with a Resistive Load

Ø NMOS Inverter with an Active Load

Ø CMOS Inverter

COMPONENTS

Ø CD4007 MOSFET array

Ø 0.01mF capacitor

Ø 3.3 kW resistors

PRELAB

The device you will use throughout this experiment is a CD4007B Transistor array. It contains three N-channel and three P-channel devices. Detailed schematic diagrams and pinouts are available on the data sheet. Please use care when working with these chips. They are very susceptible to excessive voltage and ESD (Electro-Static Damage). Do not exceed the experiment settings in an attempt to make your experiment work. The pin configuration is given in Figure 6.1. Note that you will be using the CD4007B which have a lower maximum voltage rating than the CD4007UB. The diagrams are the same for both the “B” and “UB” suffix devices. Avoid exposing the chip to ESD (electrostatic damage). This time of the year often has low relative humidities which make ESD more of an issue. Do not exceed the V_DD maximums!!!

Figure 6.1 Pin Configuration of CD4007.

Warning: Pin 14 should always be connected to the most positive dc voltage in the circuit. Pin 7 will always be connected to the most negative dc voltage in the circuit (ground)

(or else )!!!

Refer to the three circuit diagrams in Figures 6.2, 6.3, and 6.4. All will operate with a VDD = +8 volt power supply. Remember Pin 14 should always be connected to the most positive dc voltage in the circuit. Pin 7 will always be connected to the most negative dc voltage in the circuit.

You will need to arrange for an offset voltage so that V_in does not go below zero volts.

To standardize on the SPICE simulations, use VTO = 2 volts for the NMOS and -2 volts for the PMOS; λ= 0.02 volts^-1, and the default for KP and all other SPICE model parameters.

1. Set up the NMOS Inverter with a Resistive Load as shown in Figure 6.2. Use the NMOSFET connected to Pins 6, 7, and 8. Plot the transfer characteristic. Identify the saturation, ohmic, and cutoff regions of operation. Connect the input and output to the horizontal and vertical inputs (respectively) of your oscilloscope set to the x-y mode. This arrangement allows you to display the transfer characteristic of the circuit. Suggest a Q-point to obtain the largest small-signal voltage gain. Verify your experimental results with a load line and SPICE simulation. You will need your model parameters as obtained earlier in this experiment. Observe that you will need to provide a dc offset from the signal generator.

2. Set up the actively-loaded NMOS Inverter as shown in Figure 6.3. Use M1 Pins 6, 7, and 8 and M2 Pins 3, 4, and 5. Connect the input and output to the horizontal and vertical inputs (respectively) of your oscilloscope set to the x-y mode. This arrangement allows you to display the transfer characteristic of the circuit. Plot the transfer characteristic. Identify the saturation, ohmic, and cutoff regions of operation for each FET. Suggest a Q-point to obtain the largest small-signal voltage gain. Verify your experimental results with a “load line” which consists of the M2 characteristic and SPICE simulation. Compare your results with the resistively-loaded circuit. Note that this circuit is different than the depletion mode inverter circuit discussed and SPICE demonstrated in class. Observe that you will need to provide a dc offset from the signal generator.

3. Connect the CMOS inverter circuit of Figure 6.4. with the pins shown in Figure 6.4. You can also use the CMOS inverter FETS connected using Pins 9, 10, 11, and 12. Connect the input and output to the horizontal and vertical inputs (respectively) of your oscilloscope set to the x-y mode. This arrangement allows you to display the transfer characteristic of the circuit. Before connecting your function generator to the circuit input, adjust it for a 0-8 V triangular waveform at a frequency of 1 kHz. You will need to use the dc-offset control on your function generator to do this. That is an 8 volt peak-to-peak triangular wave added to a 4 volt dc offset. Observe and sketch the transfer characteristic, recording all critical values of voltage. Your report should include a PSPICE simulation of this circuit using your parameter extraction NMOS and PMOS models. Compare to the 4007 curves on the data sheets.

4. Refer to Figure 6.5. Measure the pulse response of the CMOS inverter with a capacitor C_o that has been added from the output to ground to “slow down” the output waveform so that measurements can be more easily made. Since the input of a CMOS gate is primarily capacitive, this also will provide the output behavior when a CMOS gate is driving many other CMOS gates (a capacitive load). Adjust your function generator to 0-8V square wave at a frequency of about 10 kHz, then connect it to the input. Measure the rise and fall times of V_out(t). You should be able to compute the effective value of the CMOS inverter output resistance, R_eq, from the rise and fall time measurements. Refer to what you did in Experiment 1 for a basic R-C network. Compare your measured results with a PSPICE simulation.

A few more items to think about. Compare the static power dissipation of the four circuits CMOS Inverter, NMOS Inverter with a resistive load, NMOS inverter with an active load, and the NMOS NOR gate with a resistive load) when operated as switches/inverters as opposed to amplifier operation.

Pretty soon you will be going home for Thanksgiving vacation. Given your EE major you will be expected to:

How I feel about some aspects of WINDOWS 8